Become skilled in two key aspects of SystemVerilog used to ensure quality and completeness in all Verification jobs.

What you will learn

Learn the concepts of Assertions and Functional Coverage and how to use SystemVerilog language for same

Gain hands on experience through examples and assignments

Add these key skills to your profile that are a must for getting any Verification job in current industry



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Welcome and Overview

Introduction and Overview
Test your basics

System Verilog Assertions – Basics and Sequences

Introduction to Assertions
SVA Basics – Immediate and Concurrent Assertions
SVA Basics – Sequence and Property Blocks
SequenceOperators – Repeat Operators
SequenceOperators – AND , OR
SequenceOperators -FirstMatch, Throughout and Within
SequenceOperators- if else, ended and triggered
Test your knowledge on operators
Sequences – Local Variables and Subroutines
Sequences – Sampled Value Functions
Test Your knowledge
Sequences – Lab Exercise 1

System Verilog Assertions – Properties and Clocking

SVA – Properties – Basics and Types
SVA – Recursive Properties
Clock resolution and Multiple Clock sequences
SVA – Binding and expect property
SV Assertions – Tips and Best Usages
Testing on Assertions
Assertions – Lab Exercise 2

System Verilog Functional Coverage Coding

Introduction to Coverage
SV Covergroups and Coverpoints – Basics
Coverage bins – Auto, transition, wildcard, ignore, illegal
SV Cross Coverage
Coverage options and usages
Coverage Methods, Performance, cover properties and misc
Testing Functional Coverage learning
SV Functoinal Coverage Lab Exercises

Course Wrap up and Summary

Upcoming Mini project – Creating Assertions and Coverage for SDRAM interface
Test Your skills
Summary and Wrap up