Verilog HDL Through Examples

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  • Reading time:7 mins read


Learn Verilog HDL to model digital circuits from the scratch through various examples

What you will learn

Verilog HDL

Digital Design in Verilog HDL

Description

Hey there, I welcome you all to my course ‘Verilog HDL through Examples’

Why Verilog?

1. To describe any digital system – microprocessor, memory, flip flop, Verilog is used. Hence it’s called as a hardware description language.

2. Using Verilog, we can model any electronic component and generate the schematic for the same.

3. For timing analysis and test analysis of circuits, Verilog is apt.

Highlights of the course:

1. Key differences between a programming language like C, C++ or Python and a hardware description language like Verilog, VHDL, SystemVerilog are clearly


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2. All the fundamental concepts of Verilog are explained through standard combinational and sequential circuits.

3. Learning through examples make them very simpler to learn.

4. Proper theoretical explanation is provided for each of the circuit that is implemented in verilog in this course.

5. Testbench for each design and knowing how to test and validate them.

6. Creating Finite State Machines in Verilog.

7. Download the code and design for each of the circuits in the resources section.

8. Getting to know how to use EDA Playground for Verilog coding and how to generate the output waveform using EPWave.

9. Some of the key concepts of Verilog like

Levels of Abstraction, Two types of assignments, Producing delay, generating clock, Procedural assignments are all explained clearly.

English
language

Content

Introduction

Introduction
Difference between HDL and Programming Languages

Understanding all the basic components of Verilog code

Understanding Levels of Abstraction in Digital Design
Three types of Modelling
The execution flow of a Verilog code

Writing our first code in Verilog – Example 1

Understanding Gate Level Modelling through a simple OR Gate
Difference between register and wire
Writing our first testbench
Interpreting our first output waveform

Dataflow Modelling and Behavioral Modelling for Example 1

Understanding Dataflow Modelling
Understanding the behaviour of a system to code it in Behavioral Modelling

Example 2 – Half adder design using all the three types of modelling

Implementing Half adders using Gatelevel Modelling
Implementing Half adders using Dataflow Modelling
Implementing the behaviour of Half adders

Example 3 – Full adder design using all the three types of modelling

Full Adders using Gate Level Modelling, Working of for loop
Example 3 using Dataflow Modelling

Example 4 – 4 bit Parallel Adder design in Verilog

4 bit Parallel Adder Design – Theory
Implementing a 4 bit Parallel Adder Circuit

Example 5 – Carry Look Ahead Adder in Verilog

An intuition on Propagation Delay
Design Steps for Carry look ahead adder
Verilog code for 4 bit Carry Look Ahead Adder

Example 6 – Code Converters in Verilog

Designing a BCD to Gray Code Converter {Full Design}
BCD to Gray Conversion in Verilog

Example 7 – Multiplexers and Demultiplexers in Verilog

37. All about Multiplexers
Multiplexers and Demultiplexers in Verilog
Difference between Blocking and Non Blocking type of assignments

Example 8 – Flip Flop Design in Verilog

Understanding the behavior of SR Flip Flops
Designing a SR Flip Flop in Verilog
Clock Generation in Verilog, Writing testbench for S R Flipflop
Analysing the output waveform of SR Flip Flop
D Flipflop in Verilog
Writing a testbench for D Flip Flop

Example 9 – One’s complement arithmetic (Vectors in Verilog)

Introduction to Vectors (Arrays) in Verilog
Detailed Implementation of One’s complement arithmetic in Verilog

Example 10 – Creating a FSM in Verilog

Creating a Finite State Machine in Verilog – 30 mins
Testbench for the FSM

Resources

Download the codes here!
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