Design of UART[Universal Asynchronous Receiver Transmitter], on FPGA using VHDL
What you will learn
Simulate FPGA design using logism.
design UART receiver on FPGA with vhdl code, and simulate on logism
design UART transmitter on FPGA with vhdl code, and simulate on logism
Learn how to simulate and design fpga circuits in logism
design UART transceiver on FPGA with vhdl code, and simulate on logism
Description
This is a practical course, that will teach you how to design your first project on FPGA [UART – universal asynchronous transmitter and receiver.]
It explains how the vdhl code was designed. and will teach you how it was simulated , and how to trace the signals for debugging using Logism.
The course is divided into three sections: the receiver, the baud generator and transmitter.
This a 12 video course. each module teaching about a particular part of the design.
a lot of visuals, arrows, pictures were used to make the tutorials easy to understand.
kindly use the logism circuit file while watching the tutorial for easy understanding.
if my english is too fast please use the subtitle files attached.
You will design a uart transmitter and receiver . You will be able to design a transceiver by the end of the course. You will get the VHDL scripts and the logism circuit. subsequent courses will teach other serial communication protocols spi, i2c , encryption algorithm includng aes, sha256, RSA, ECDSA. Basic knowledge of vdhl is required.
View upcoming projects at projectfpga.
While on the course please download the attached files, and check links for downloads. they include logism circuit files, vhdl script. etc.
No hardware is required just your pc.
It was kept brief and straight to the point.