Learn VHDL from the beginning for FPGA and CPLD development

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Learn VHDL programming language for FPGA, learn basics of FPGA in this VHDL online course with exercises

What you will learn

How to write the VHDL code from zero

Fundamentals of FPGA and CPLD

Everything needed in order to become an FPGA engineer

Solving out 6 exercises and learn by examples

How to Simulate your VHDL design

Upload the VHDL code to a real FPGA with development board

VHDL structure, types, variables and how to write the code right

Description

This VHDL Course was made by a professional electronic engineer specializes in FPGA !

In this VHDL course you will learn how to write VHDL code for FPGAs/CPLDs development and become a professional FPGA developer


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  • No prior VHDL or FPGA knowledge is needed. This VHDL course is designed from the basic elements you need to know about VHDL code.

    The VHDL course built in such way that you will learn first about the FPGAs and CPLDs structure so you will have a basic knowledge what are you going to do when you are writing a VHDL code.

Students saying:

  • N Venkata Bhaskar: “The course is very proper to beginner level in VHDL. you can learn a lot of topics.Excellent explanation and easy to understand examples on FPGA.“
  • Umesh kumar Sharma: “very well explained…covered all concepts step by step with examples.“
  • We will go through all the basic elements of the VHDL code

    Starting from the VHDL code structure of a basic code to the structure of more advanced coding.

    After learning about the structure you will learn about the data types, VHDL basic design units, VHDL advanced design units, VHDL statements format.

  • You will learn about the Clock and Resets of the FPGA and how to use them

    FPGAs/CPLDs are actual components that receiving real signals from the outside world. Some of them will be synchronized signals that has a clock. You will learn how to use the clocks and the resets to sample new data and create data/communication with the outside world.

  • The course contains over 50 lectures that will teach you the syntax of the VHDL code
  • In the end of the VHDL course we will complete together 6 Exercises

    You will learn how to code the VHDL by practice. Starting from the most basic VHDL code with Increasing task difficulty enhances I will show you in these videos how to write the code in the right way.

  • In the end of the VHDL course I will upload the last exercise code to a real FPGA! (with my Xilinx development board)

    I will also show you in real-time how I can debug the code with a real time debugger which is the Integrated logic analyzer of Xilinx.

This VHDL Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market.

English
language

Content

Introduction

Introduction
FPGA and CPLD Architectures
VHDL introduction

Structure of VHDL language code

Structure of a basic VHDL code

VHDL Data types and operators

FPGA Port modes
Data Types
Array and Record
Signal and Variable
Operators
Attributes
Alias

VHDL Basic Design Units

Entity
Architecture
Component
Process
Library

VHDL extra unit design

Generic
Functions and procedures
Block
Package and Package body
Configuration

VHDL programming format- Statements

Declaration statements
Concurrent statements
Concurrent statements – signal assignment statement
Concurrent Statement – Generate statement
Sequential statements
Sequential statements – IF statement
Sequential statements – Case statement
Sequential statements – Loop statement
Sequential statements – While statement
Sequential statements – Wait statement

Clocked processes

Create a Flip-Flop
Latches
Resets
Variable vs Signal in a clocked process

State machines

Moore state machine
Mealy state machine
One hot enumeration

Exercises

Exercise 1: Simple AND gate
Exercise 2: N Bit up counter
Simulation for Exercise 2
Exercise 3: 8 Bit Shift Left register
Exercise 4: Single RAM memory
Exercise 5 part1: Delay an Input by 10uS
Exercise 5 part2: Traffic Light State machine with the Delay component
Simulation for Exercise 5

Implementing the code to a real FPGA

Running the code on a real FPGA
Simulate the code with a real-time debugger – The logic analyzer tool

Extras

Bonus Lecture
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