From a DVCon event

Description

UVM is the most widely used verification methodology in the field of ASIC and FPGA designs. It truly justifies its expanded name as – Universal Verification Methodology – as it serves the needs of various types of design styles, users etc. In this course we present UVM from an RTL designers’ use-model with carefully chosen problems and solutions that are tailored towards simple use model. No prior exposure to UVM is assumed. We do break the stigma around UVM projecting it as complex for simple-use-cases. Below is what we cover in this course:

1. UVM For RTL Designers – introduction, problem statement

2. Typical care-abouts of RTL designers for quick, sanity checking before handing over to a full-fledged verification team

3. Simple FIFO DUT as vehicle to explain UVM adoption

4. Go2UVM open-source layer

5. Go2UVM generator app to generate skeleton code for a given RTL

6. Wave2UVM app – to convert WaveDrom files to UVM tests

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7. Register Verification app – a demo to show how quickly sanity checking of registers can be done

8. Q&A sessions

The entire material is captured from a live presentation at DVCon event. The sessions are split as logically as possible, but given the live recording, there are certain overlaps and we request the audience to bear with the same. Also at times the pace of the talk is little faster than what we wish, but in case you need to, please use the speed settings to adjust.

English

Language

Content

Welcome to CVC training!

Welcome to CVC training!

Introduction


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Introduction

UVM in nutshell

UVM in nutshell

Using productivity apps on top of UVM

Xilinx + Go2UVM app, Wave2UVM app and Register Verification

Register Verification simplified with UVM

Register Verification simplified with UVM

Checker Library – for RTL designers and Conclusion

Checker Library – for RTL designers and Conclusion

Summary, Q&A Part-1

Summary, Q&A Part-1

Q&A Part-2

Q&A Part-2