Unveiling UVM in SystemVerilog language: From Building UVM Agents to Functional Coverage and Debugging Techniques
What you will learn
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Module level verification using SystemVerilog and UVM library.
Build agents in SystemVerilog/UVM to drive and monitor communication interfaces.
Build the model of the registers using UVM and connect it to the APB interface in order to let UVM perform its automatic checks on the register accesses.
Build the functional model of a Device Under Test (DUT) and use it to predict the correct response expected from the DUT.
Build a scoreboard to verify automatically all the expected outputs of a DUT.
Build the coverage model and all the logic necessary to collect that coverage.
Build random tests to verify all the features of a DUT.
Learn how to deal with synchronization issues in the model.
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